IEEE - Institute of Electrical and Electronics Engineers, Inc. - On-chip interconnect modeling technologies

Electrical Performance of Electronic Packaging

Author(s): Dengi, E.A. ; Rohrer, R.A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: San Jose, CA, USA, USA
Conference Date: 27 October 1997
ISBN (Paper): 0-7803-8649-3
DOI: 10.1109/EPEP.1997.634034
Regular:

Summary form only given. On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Each level... View More

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