IEEE - Institute of Electrical and Electronics Engineers, Inc. - Delta-I noise avoidance methodology for high performance chip designs [CMOS microprocessors]

Electrical Performance of Electronic Packaging

Author(s): Cases, M. ; Singh, B. ; Smith, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: San Jose, CA, USA, USA
Conference Date: 27 October 1997
Page(s): 27 - 30
ISBN (Paper): 0-7803-8649-3
DOI: 10.1109/EPEP.1997.634030
Regular:

A methodology which controls induced di/dt noise for high performance chip designs is described. Delta-I modeling and analysis for the chip, module and card is used to define a strategy and... View More

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