IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design methodology for chip-on-chip applications

Electrical Performance of Electronic Packaging

Author(s): Low, Y.L. ; Frye, R.C. ; O'Connor, K.J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: San Jose, CA, USA, USA
Conference Date: 27 October 1997
Page(s): 5 - 8
ISBN (Paper): 0-7803-8649-3
DOI: 10.1109/EPEP.1997.634024
Regular:

We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system.

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