IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design Methodology For Optimizing Gate Driven ESD Protection Circuits In Submicron Cmos Processes

Proceedings of 18th Annual Electrical Overstress/Electrostatic Discharge Symposium

Author(s): Julian Zhiliang Chen ; Amerasekera, A. ; Duvvury, C.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Santa Clara, California, USA, USA
Conference Date: 23 September 1997
Page(s): 230 - 239
ISBN (Paper): 1-878303-69-4
DOI: 10.1109/EOSESD.1997.634247
Regular:

This report describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS) protection scheme has been presented. Without requiring... View More

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