IEEE - Institute of Electrical and Electronics Engineers, Inc. - An approach for detecting bridging fault-induced delay faults in static CMOS circuits using dynamic power supply current monitoring

Digest of Papers IEEE International Workshop on IDDQ Testing

Author(s): A. Walker ; P.K. Lala
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Test Technol
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Washington, DC, USA, USA
Conference Date: 5 November 1997
Page Count: 5
Page(s): 73 - 77
ISBN (Paper): 0-8186-8123-3
DOI: 10.1109/IDDQ.1997.633017
Regular:

A new approach for the detection of bridging fault-induced delay faults in static CMOS logic circuits is presented in this paper. It is based upon the transient current that is sourced (or sink)... View More

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