IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimising designs for hardware compilation to FPGAs

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

Author(s): O'Reilly, F.J. ; Marnane, W.P. ; Murphy, P.J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Leicester, UK, United Kingdom
Conference Date: 5 November 1997
Page(s): 522 - 531
ISBN (Paper): 0-7803-3806-5
ISSN (Paper): 1520-6130
DOI: 10.1109/SIPS.1997.626342
Regular:

Field programmable gate arrays with their re-configurable architectures are a powerful tool for implementing re-configurable computing. Using the facility of re-programmability, designs can be... View More

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