IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fast VLSI binary addition

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

Author(s): Parhi, K.K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Leicester, UK, United Kingdom
Conference Date: 5 November 1997
Page(s): 232 - 241
ISBN (Paper): 0-7803-3806-5
ISSN (Paper): 1520-6130
DOI: 10.1109/SIPS.1997.626129
Regular:

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is... View More

Advertisement