IEEE - Institute of Electrical and Electronics Engineers, Inc. - Eutectic solder bump process for ULSI flip chip technology

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium

Author(s): Ezawa, H. ; Miyata, M. ; Inoue, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Austin, TX, USA
Conference Date: 13 October 1997
Page(s): 293 - 298
ISBN (Paper): 0-7803-3929-0
ISSN (Paper): 1089-8190
DOI: 10.1109/IEMT.1997.626934
Regular:

A novel eutectic solder bump process, which allows ULSI chips area array pad layout, has been developed. Straight side wall bumps as plated using a new negative-type photoresist and eutectic... View More

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