IEEE - Institute of Electrical and Electronics Engineers, Inc. - Functional fault simulation of VHDL gate level models

Proceedings VHDL International Users' Forum. Fall Conference

Author(s): Aftabjahani, S.A. ; Navabi, Z.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Arlington, VA, USA, USA
Conference Date: 19 October 1997
Page(s): 18 - 23
ISBN (Paper): 0-8186-8180-2
DOI: 10.1109/VIUF.1997.623925
Regular:

A method of fault injection and fault simulation is proposed. A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new... View More

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