IEEE - Institute of Electrical and Electronics Engineers, Inc. - Using WAVES for verification of synthesized sub-components in a deeply hierarchical design

Proceedings VHDL International Users' Forum. Fall Conference

Author(s): Kadrovach, B. ; Jarusiewic, P. ; Read, B. ; Bishop, R. ; Concha, L. ; Olson, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Arlington, VA, USA, USA
Conference Date: 19 October 1997
Page(s): 11 - 17
ISBN (Paper): 0-8186-8180-2
DOI: 10.1109/VIUF.1997.623924
Regular:

The Waveform and Vector Exchange Standard (WAVES) and organically developed tools were used in a new testing and verification methodology for an in-house design of a massively parallel graphics... View More

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