IEEE - Institute of Electrical and Electronics Engineers, Inc. - Adding instruction cache effect to schedulability analysis of preemptive real-time systems

Proceedings Real-Time Technology and Applications

Author(s): Busquets-Mataix, J.V. ; Serrano, J.J. ; Ors, R. ; Gil, P. ; Wellings, A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Brookline, MA, USA, USA
Conference Date: 10 June 1996
Page(s): 204 - 212
ISBN (Paper): 0-8186-7448-2
DOI: 10.1109/RTTAS.1996.509537
Regular:

Cache memories are commonly avoided in real time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time... View More

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