IEEE - Institute of Electrical and Electronics Engineers, Inc. - A ternary systolic product-sum circuit for GF(3/sup m/) using neuron MOSFETs

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96)

Author(s): Muranaka, N. ; Arai, S. ; Imanishi, S. ; Miller, D.M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Santiago de Compostela, Spain, Spain
Conference Date: 29 May 1996
Page(s): 92 - 97
ISBN (Paper): 0-8186-7392-3
ISSN (Paper): 0195-623X
DOI: 10.1109/ISMVL.1996.508342
Regular:

In this paper, we present a ternary systolic product-sum computation circuit for GF(3/sup m/) using voltage-mode neuron MOSFETs. The required subcircuits are discussed which together form a basic... View More

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