IEEE - Institute of Electrical and Electronics Engineers, Inc. - Exploring multiplier architecture and layout for low power

Proceedings of Custom Integrated Circuits Conference

Author(s): Meier, P.C.H. ; Rutenbar, R.A. ; Carley, L.R.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: San Diego, CA, USA, USA
Conference Date: 5 May 1996
Page(s): 513 - 516
ISBN (Paper): 0-7803-3117-6
DOI: 10.1109/CICC.1996.510609
Regular:

Multiplication represents a fundamental building block in all DSP tasks. Due to the large latency inherent in multiplication, schemes have been devised to minimize the delay. Two methods are... View More

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