IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient area minimization for dynamic CMOS circuits

Proceedings of Custom Integrated Circuits Conference

Author(s): Basaran, B. ; Rutenbar, R.A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: San Diego, CA, USA, USA
Conference Date: 5 May 1996
Page(s): 505 - 508
ISBN (Paper): 0-7803-3117-6
DOI: 10.1109/CICC.1996.510607
Regular:

We present a new transistor ordering technique for the layout of dynamic CMOS leaf-cells which minimizes the cell area. The technique employs an Eulerian trail formulation which guarantees that... View More

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