IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimization of standard cell libraries for low power, high speed, or minimal area designs

Proceedings of Custom Integrated Circuits Conference

Author(s): Fisher, C. ; Blankenship, R. ; Jensen, J. ; Rossman, T. ; Svilich, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: San Diego, CA, USA, USA
Conference Date: 5 May 1996
Page(s): 493 - 496
ISBN (Paper): 0-7803-3117-6
DOI: 10.1109/CICC.1996.510604
Regular:

A methodology for optimization of device sizes in CMOS standard cell libraries is described. The libraries are generated by compilers that allow for design rule and device size parameterization.... View More

Advertisement