IEEE - Institute of Electrical and Electronics Engineers, Inc. - An 8-bit 50+ Msamples/s pipelined A/D converter with an area and power efficient architecture

Proceedings of Custom Integrated Circuits Conference

Author(s): Nagaraj, K. ; Fetterman, H.S. ; Shariatdoust, R.S. ; Anidjar, J. ; Lewis, S.H. ; Alsayegh, J. ; Renninger, R.G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: San Diego, CA, USA, USA
Conference Date: 5 May 1996
Page(s): 423 - 426
ISBN (Paper): 0-7803-3117-6
DOI: 10.1109/CICC.1996.510589
Regular:

An efficient architecture for a pipelined A/D converter is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-bit converter... View More

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