IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 35 Gbit/s throughput 64 kbit CMOS buffer SRAM

Proceedings of Custom Integrated Circuits Conference

Author(s): Alowersson, J. ; Andersson, P.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: San Diego, CA, USA, USA
Conference Date: 5 May 1996
Page(s): 261 - 264
ISBN (Paper): 0-7803-3117-6
DOI: 10.1109/CICC.1996.510555
Regular:

A 64 kbit 0.8-/spl mu/m pure CMOS buffer memory with 256 bit word-length and 3.6 ns cycle time, allowing 35 Gbit/s throughput, is presented. The memory consumes 1.5 W at the maximum frequency. The... View More

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