IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 1860 kG CMOS gate array with GTL input flip-flop circuits

Proceedings of Custom Integrated Circuits Conference

Author(s): Tomobe, K. ; Takahashi, T. ; Kawashima, M. ; Sonobe, Y. ; Kiyuna, T. ; Yamamoto, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: San Diego, CA, USA, USA
Conference Date: 5 May 1996
Page(s): 61 - 64
ISBN (Paper): 0-7803-3117-6
DOI: 10.1109/CICC.1996.510512
Regular:

A 1860 kG CMOS gate array with a high speed I/O circuit using 0.35 /spl mu/m CMOS process technology, has been developed. 300 MHz synchronous data transmission through a 30 cm line has been... View More

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