IEEE - Institute of Electrical and Electronics Engineers, Inc. - A proven methodology for designing one-million-gate ASICs

Proceedings of Custom Integrated Circuits Conference

Author(s): Rincon, A.M. ; Trick, M. ; Guzowski, T.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: San Diego, CA, USA, USA
Conference Date: 5 May 1996
Page(s): 45 - 52
ISBN (Paper): 0-7803-3117-6
DOI: 10.1109/CICC.1996.510509
Regular:

This paper describes the methodology used to design a family of ASIC chips in the 400 K to one-million-gate range in a 0.5 micron technology. Working first-pass hardware was produced at an average... View More

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