IEEE - Institute of Electrical and Electronics Engineers, Inc. - Boron sidewall implantation and selective etching of p-doped poly-Si for 1 Gbit DRAM stacked capacitors

1996 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): H. Wendt ; W. Honlein ; M. Franosch ; D. Widmann
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1996
Conference Location: Honolulu, HI, USA, USA
Conference Date: 11 June 1996
Page Count: 2
Page(s): 212 - 213
ISBN (Paper): 0-7803-3342-X
DOI: 10.1109/VLSIT.1996.507854
Regular:

It is generally accepted that a minimum cell capacitance of about 25 fF is necessary for DRAMs. In order to allow for lateral shrinking of the cell sizes while keeping the required cell... View More

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