IEEE - Institute of Electrical and Electronics Engineers, Inc. - Yield analysis and optimization of VLSI interconnects in multichip modules

Proceedings of IEEE Multi-Chip Module Conference (MCMC-93)

Author(s): Zhang, Q.J. ; Nakhla, M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Santa Cruz, CA, USA, USA
Conference Date: 15 May 1993
Page(s): 160 - 163
ISBN (Paper): 0-8186-3540-1
DOI: 10.1109/MCMC.1993.302134
Regular:

A CAD approach integrating multidimensional correlated Monte-Carlo analysis and generalized l/sub 1/ optimization with lossy transmission line network simulations is presented. It is implemented... View More

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