IEEE - Institute of Electrical and Electronics Engineers, Inc. - Gate model networks for minimization of multiple-valued logic functions

Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

Author(s): Hata, Y. ; Hozumi, T. ; Yamato, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Sacramento, CA, USA
Conference Date: 24 May 1993
Page(s): 29 - 34
ISBN (Paper): 0-8186-3350-6
DOI: 10.1109/ISMVL.1993.289585
Regular:

The use of gate model networks as a logic minimization method for multiple-valued logic functions is proposed. The gate model network is a kind of neural network constructed like and AND-OR... View More

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