IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of set-valued logic networks for wave-parallel computing

Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

Author(s): Yuminaka, Y. ; Aoki, T. ; Higuchi, T.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Sacramento, CA, USA
Conference Date: 24 May 1993
Page(s): 277 - 282
ISBN (Paper): 0-8186-3350-6
DOI: 10.1109/ISMVL.1993.289547
Regular:

A design for set-valued logic (SVL) networks that provides a solution to interconnection problems in highly parallel VLSI systems is presented. The basic concept is frequency multiplexing of logic... View More

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