IEEE - Institute of Electrical and Electronics Engineers, Inc. - A high precision (+/- 100 ppm) CMOS clock generator for optimum sampling of analog RGB data [in LCD panel display]

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

Author(s): Terukina, A. ; Nozawa, T. ; Suzuki, Y. ; Hino, A. ; Koyama, S. ; Moritani, A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: San Diego, CA, USA
Conference Date: 9 May 1993
ISBN (Paper): 0-7803-0826-3
DOI: 10.1109/CICC.1993.590803
Regular:

An integrated timing generator composed of variable delay line and PLL (phase-locked-loop) is described. To determine the sampling point for video analog data, a pixel clock is regenerated from an... View More

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