IEEE - Institute of Electrical and Electronics Engineers, Inc. - 0.3 /spl mu/m mixed analog/digital CMOS technology for low-voltage operation

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

Author(s): Miyamoto, M. ; Ishii, T. ; Nagai, R. ; Nishida, T. ; Seki, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: San Diego, CA, USA
Conference Date: 9 May 1993
ISBN (Paper): 0-7803-0826-3
DOI: 10.1109/CICC.1993.590764
Regular:

A 0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation is developed, including a novel MOSFET structure with laterally doped buried (LDB) layer and a... View More

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