IEEE - Institute of Electrical and Electronics Engineers, Inc. - Technology mapping and circuit depth optimization for field programmable gate arrays

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93

Author(s): Shih-Chieh Chang ; M. Marek-Sadowska
Sponsor(s): IEEE Electron. Devices Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: San Diego, CA, USA, USA
Conference Date: 9 May 1993
Page Count: 4
ISBN (Paper): 0-7803-0826-3
DOI: 10.1109/CICC.1993.590373
Regular:

A two-step technology mapping algorithm for lookup-table-type FPGAs (field programmable gate arrays) is proposed. In the first step, the technology mapper attempts to minimize the total number of... View More

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