IEEE - Institute of Electrical and Electronics Engineers, Inc. - Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

Author(s): Lowe, K.S. ; Gulak, P.G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Santa Clara, CA, USA, USA
Conference Date: 7 November 1993
Page(s): 216 - 219
ISBN (Paper): 0-8186-4490-7
DOI: 10.1109/ICCAD.1993.580059
Regular:

This paper presents a method for optimizing BiCMOS logic networks that exploits the fact that such networks may use a mixture of both CMOS and BiCMOS gates. The method assumes a given network... View More

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