IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and implementation of an area and time efficient systolic parallel Booth multiplier

Proceedings of 36th Midwest Symposium on Circuits and Systems

Author(s): Panneerselvam, G. ; Nowrouzian, B.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Detroit, MI, USA
Conference Date: 16 August 1993
ISBN (Paper): 0-7803-1760-2
DOI: 10.1109/MWSCAS.1993.343398
Regular:

This paper presents combined area-efficient and time-efficient systolic architectures for parallel Booth multiplication. These systolic architectures employ composite (instead of fine grained)... View More

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