IEEE - Institute of Electrical and Electronics Engineers, Inc. - A scan design for asynchronous sequential logic circuits using SR-latches

Proceedings of 36th Midwest Symposium on Circuits and Systems

Author(s): Ming-Der Shieh ; Chin-Long Wey ; Fisher, P.D.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Detroit, MI, USA
Conference Date: 16 August 1993
ISBN (Paper): 0-7803-1760-2
DOI: 10.1109/MWSCAS.1993.343339
Regular:

This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the... View More

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