IEEE - Institute of Electrical and Electronics Engineers, Inc. - A systolic computation scheme of time-delay neural networks

Proceedings of 36th Midwest Symposium on Circuits and Systems

Author(s): Perez-Castellanos, M. ; Rodellar, V. ; Bobadilla, J. ; Peinado, V. ; Gomez-Vilda, P.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Detroit, MI, USA
Conference Date: 16 August 1993
ISBN (Paper): 0-7803-1760-2
DOI: 10.1109/MWSCAS.1993.343275
Regular:

The basic idea developed in this paper is to study the viability of computing a TDNN algorithm in a systolic architecture. The main problem to adopt this kind of solution resides in the presence... View More

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