IEEE - Institute of Electrical and Electronics Engineers, Inc. - A cache coherency scheme for an asynchronous packet-switched shared memory multiprocessor

Proceedings of 36th Midwest Symposium on Circuits and Systems

Author(s): Alles, S. ; Mahmud, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Detroit, MI, USA
Conference Date: 16 August 1993
ISBN (Paper): 0-7803-1760-2
DOI: 10.1109/MWSCAS.1993.343101
Regular:

This paper analyses the problems encountered in designing a bus-based cache coherence protocol for an asynchronous packet switched multiprocessor system having private caches for each processor... View More

Advertisement