IEEE - Institute of Electrical and Electronics Engineers, Inc. - A VLSI architecture for DFT

Proceedings of 36th Midwest Symposium on Circuits and Systems

Author(s): Chan, E. ; Panchanathan, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Detroit, MI, USA
Conference Date: 16 August 1993
ISBN (Paper): 0-7803-1760-2
DOI: 10.1109/MWSCAS.1993.343072
Regular:

In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC's) and requires N clock... View More

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