IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimum area minimization for nonslicing floorplan [VLSI layout]

Proceedings of 36th Midwest Symposium on Circuits and Systems

Author(s): Kai Wang ; Wai-Kai Chen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Detroit, MI, USA
Conference Date: 16 August 1993
ISBN (Paper): 0-7803-1760-2
DOI: 10.1109/MWSCAS.1993.343005
Regular:

In this paper, we propose a new algorithm to solve the floorplan area optimization problem for all implementations of each module. By using slicing and extended slicing techniques, we decompose a... View More

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