IEEE - Institute of Electrical and Electronics Engineers, Inc. - Delay modelling and optimization of BiCMOS buffer circuits

Proceedings of 36th Midwest Symposium on Circuits and Systems

Author(s): Esonu, M.O. ; Al-Khalili, D. ; Al-Khalili, A.J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Detroit, MI, USA
Conference Date: 16 August 1993
ISBN (Paper): 0-7803-1760-2
DOI: 10.1109/MWSCAS.1993.342983
Regular:

In this work the analytical delay expressions for BiCMOS buffer circuits are presented. The equations contain device geometrical and other process parameters, and can be used to calculate the rise... View More

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