IEEE - Institute of Electrical and Electronics Engineers, Inc. - Multiprocessor design using joint transform correlator

Proceedings of NAECON '93 - National Aerospace and Electronics Conference

Author(s): Alam, M.S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: Dayton, OH, USA
Conference Date: 24 May 1993
ISBN (Paper): 0-7803-1295-3
DOI: 10.1109/NAECON.1993.290794
Regular:

The joint transform correlation technique is used to design a binary multiprocessor that can perform full addition and full subtraction in parallel. A new coding scheme is designed for the... View More

Advertisement