IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '93

Author(s): Tamba, N. ; Akimoto, K. ; Ohhayashi, M. ; Hiramoto, T. ; Kokubu, T. ; Ohmori, S. ; Muraya, T. ; Kishimoto, A. ; Tsuji, S. ; Hayashi, H. ; Handa, H. ; Igarashi, T. ; Fujiwara, T. ; Watanabe, K. ; Uchida, A. ; Odaka, M. ; Nambu, H. ; Yamaguchi, K. ; Ikeda, T.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1993
Conference Location: San Francisco, CA, USA, USA
Conference Date: 24 February 1993
Page(s): 246 - 247
ISBN (Paper): 0-7803-0987-1
DOI: 10.1109/ISSCC.1993.280029
Regular:

The authors present a chip with 1.5-ns access SRAM (static random access memory) and 60-ps logic gates that uses a BiCMOS memory technology with ECL (emitter coupled logic)-CMOS circuits and a... View More

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