IEEE - Institute of Electrical and Electronics Engineers, Inc. - 0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

Author(s): Hara, H. ; Sakurai, T. ; Noda, M. ; Nagamatsu, T. ; Kobayashi, S. ; Seta, K. ; Momose, H. ; Niitsu, Y. ; Miyakawa, H. ; Maeguchi, K. ; Watanabe, Y. ; Sano, F.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Conference Location: San Francisco, CA, USA, USA
Conference Date: 13 February 1991
Page(s): 148 - 307
ISBN (Paper): 0-87942-644-6
DOI: 10.1109/ISSCC.1991.689103
Advertisement