IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 45ns 64Mb DRAM With A Merged Match-line Test Architecture

Author(s): Mori, S. ; Miyamoto, H. ; Morooka, Y. ; Kikuda, S. ; Suwa, M. ; Kinoshita, M. ; Hachisuka, A. ; Arima, H. ; Yamada, M. ; Yoshihara, T. ; Kayano, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Conference Location: San Francisco, CA, USA, USA
Conference Date: 13 February 1991
Page(s): 110 - 298
ISBN (Paper): 0-87942-644-6
DOI: 10.1109/ISSCC.1991.689085
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