IEEE - Institute of Electrical and Electronics Engineers, Inc. - Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Author(s): Fujita, M. ; Matsunaga, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Conference Location: Santa Clara, CA, USA, USA
Conference Date: 11 November 1991
Page(s): 560 - 563
ISBN (Paper): 0-8186-2157-5
DOI: 10.1109/ICCAD.1991.185332
Regular:

The authors present a method for multilevel logic minimization which is particularly suitable for the minimization of look-up table type FPGAs (field programmable gate arrays). Given a set of... View More

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