IEEE - Institute of Electrical and Electronics Engineers, Inc. - Delay optimization of combinational logic circuits by clustering and partial collapsing

Author(s): Touati, H.J. ; Savoj, H. ; Brayton, R.K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Conference Location: Santa Clara, CA, USA, USA
Conference Date: 11 November 1991
Page(s): 188 - 191
ISBN (Paper): 0-8186-2157-5
DOI: 10.1109/ICCAD.1991.185227
Regular:

The authors propose a novel technology-independent algorithm to minimize circuit delay. The algorithm works in two steps. The first step performs a partial collapse of the circuit based on... View More

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