IEEE - Institute of Electrical and Electronics Engineers, Inc. - Layout-area models for high-level synthesis

Author(s): Wu, A.C.-H. ; Chaiyakul, V. ; Gajski, D.D.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Conference Location: Santa Clara, CA, USA, USA
Conference Date: 11 November 1991
Page(s): 34 - 37
ISBN (Paper): 0-8186-2157-5
DOI: 10.1109/ICCAD.1991.185184
Regular:

The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for... View More

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