IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fault-tolerant parallel matrix multiplication with one iteration fault detection latency

Author(s): Hong, C.-E. ; McMillin, B.M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Conference Location: Tokyo, Japan
Conference Date: 11 September 1991
Page(s): 665 - 672
ISBN (Paper): 0-8186-2152-4
DOI: 10.1109/CMPSAC.1991.170258
Regular:

A new algorithm, the ID algorithm, is presented which minimizes the fault-detection latency. In the ID algorithm, a fault is detected as soon as the fault occurs instead of at problem termination.... View More

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