IEEE - Institute of Electrical and Electronics Engineers, Inc. - An architectural level test generator for a hierarchical design environment

Author(s): Lee, J. ; Patel, J.H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1991
Conference Location: Montreal, Que., Canada
Conference Date: 25 June 1991
Page(s): 44 - 51
ISBN (Paper): 0-8186-2150-8
DOI: 10.1109/FTCS.1991.146631
Regular:

Most state-of-the-art automatic test pattern generators (ATPGs) require a detailed gate level representation for the circuits under test, information that either does not exist or may not be... View More

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