IEEE - Institute of Electrical and Electronics Engineers, Inc. - DFT standards allow optimized tester configuration to reduce cost of test

Author(s): LaBuda, V.P. ; Youngblood, R.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: Rochester, NY, USA
Conference Date: 17 September 1990
DOI: 10.1109/ASIC.1990.186183
Regular:

High-pin-count testers for silicon employing design-for-testability (DFT) techniques are examined as they relate to facilitating low-cost test of application-specific integrated... View More

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