IEEE - Institute of Electrical and Electronics Engineers, Inc. - A pipelined ASIC for color matrixing and convolution

Author(s): Hsu, K. ; D'Luna, L.J. ; Yeh, H. ; Cook, W.A. ; Brown, G.W.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: Rochester, NY, USA
Conference Date: 17 September 1990
DOI: 10.1109/ASIC.1990.186140
Regular:

A VLSI chip that can perform either 3*3 matrix multiplication or 3*3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high... View More

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