IEEE - Institute of Electrical and Electronics Engineers, Inc. - Managing risk in ASIC design cycle

Author(s): Zafar, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: Rochester, NY, USA
Conference Date: 17 September 1990
DOI: 10.1109/ASIC.1990.186093
Regular:

ASIC design validation, confirming that the chips work in the system, has been the major source of risk in any ASIC development cycle. The risk is that of missing the market window. The cause is... View More

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