IEEE - Institute of Electrical and Electronics Engineers, Inc. - A bipolar-EPROM (BI-EPROM) structure for 3.3 V operation and high speed application

Author(s): Matsukawa, N. ; Masuda, K. ; Miyamoto, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: San Francisco, CA, USA, USA
Conference Date: 9 December 1990
Page(s): 313 - 316
ISSN (Paper): 0163-1918
DOI: 10.1109/IEDM.1990.237167
Regular:

A novel BI-EPROM structure, which has a vertical PNP bipolar transistor in the drain of the conventional EPROM cell, is proposed for future low-voltage and high-speed nonvolatile memories. In the... View More

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