IEEE - Institute of Electrical and Electronics Engineers, Inc. - 4-layer 3-D IC technologies for parallel signal processing

Author(s): Yamazaki, K. ; Itoh, Y. ; Wada, A. ; Morimoto, K. ; Tomita, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: San Francisco, CA, USA, USA
Conference Date: 9 December 1990
Page(s): 599 - 602
ISSN (Paper): 0163-1918
DOI: 10.1109/IEDM.1990.237127
Regular:

A four-layer 3-D device used for parallel image signal processing was fabricated as an example of a primitive 3-D device. SOI (silicon-on-insulator) layers were formed by laser... View More

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