IEEE - Institute of Electrical and Electronics Engineers, Inc. - Automatic incorporation of on-chip testability circuits

Author(s): Ito, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: Orlando, FL, USA, USA
Conference Date: 24 June 1990
Page(s): 529 - 534
ISBN (Paper): 0-89791-363-9
ISSN (Paper): 0738-100X
DOI: 10.1109/DAC.1990.114912
Regular:

A system which automatically incorporates testability circuits into ECL chips is presented. Three types of circuits are incorporated: (1) a random access scan circuit, (2) a clock suppression... View More

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