IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reduced offsets for two-level multi-valued logic minimization

Author(s): Malik, A.A. ; Brayton, R.K. ; Newton, A.R. ; Sangiovanni-Vincentelli, A.L.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1990
Conference Location: Orlando, FL, USA, USA
Conference Date: 24 June 1990
Page(s): 290 - 296
ISBN (Paper): 0-89791-363-9
ISSN (Paper): 0738-100X
DOI: 10.1109/DAC.1990.114869
Regular:

The approaches to two-level logic minimization can be classified into two groups: those that use tautology for expansion of cubes and those that use the offset Tautology-based schemes are... View More

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